1. Field of the Invention
The present invention relates to a multi-chip package structure. More particularly, the present invention relates to a multi-chip package structure having a patterned lamination layer capable of improving reliability.
2. Description of Related Art
With the progressive advancement of electronic technology, miniaturization of electronic products has become increasingly important. This miniaturization results in a more complicated and denser structure of electronic products. In electronic industries, the packaging of electronic devices thus requires package structures that have small dimensions and high density. In this context, many types of packaging structures are being developed, such as ball grid array (BGA) packages, chip-scale packages (CSP), flip-chip (F/C) packages, multi-chip module (MCM) packages, etc. Among the above-mentioned types of packaging structures, the flip-chip packages advantageously allow for a packaging structure that has a small size, high pin counts, a short signal path, a low induction and a control of noise signals. Thus, the flip-chip structure is widely used in packaging electronic devices.
Recently, IC manufacturers propose some die-to-die packages. In the die-to-die package, at least one passive component or chip having low pin-counts is disposed face-to-face on a chip having high pin-counts, wherein the chips are electrically connected to each other through conductive bumps. Moreover, the chips are electrically connected to each other through solder bumps, and the chip having high pin-counts is electrically connected to a carrier through bumps or bonding wires.
FIG. 1 is a schematic cross-sectional view of a conventional multi-chip package structure. Referring to FIG. 1, a conventional multi-chip package structure 100 is electrically connected to a carrier 50. The multi-chip package structure 100 includes a first chip 110, a plurality of first bumps 130, a second chip 140 and a plurality of second bumps 150. The first chip 110 has a first active surface 112, wherein a plurality of first bonding pads 114 and second bonding pads 116 are disposed on the first active surface 112. The first bumps 130 are disposed on the first bonding pads 114 and electrically connected to the carrier 50. The second chip 140 has a second active surface 142, wherein a plurality of third bonding pads 144 is disposed on the second active surface 142. Furthermore, the third bonding pads 144 are electrically connected to the second bonding pads 116 through the second bumps 150.
As mentioned above, since the space for accommodating the second chip 140 and the second bumps 150 is limited by the height of the first bumps 130, reliability of the connection between the first chip 110 and the second chip 140 is deteriorated. Therefore, feasibility of manufacturing the multi-chip package structure 100 is reduced significantly.